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19-2389; Rev 3; 3/06
Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer
General Description
The MAX2150 is a complete wideband direct upconversion quadrature modulator IC incorporating a 28-bit sigma-delta fractional-N synthesizer. The device is targeted for applications in the 700MHz to 2300MHz frequency range. The super-high-resolution sigma-delta fractional-N synthesizer is capable of better than 50mHz resolution when used with a 10MHz reference. Other features: fully differential I/Q modulation inputs, an internal LO buffer, and a 50 wideband output driver amplifier. A standard 3-wire interface is provided for synthesizer programming and overall device configuration. An onchip low-noise crystal oscillator amplifier is also included and can be configured as a buffer when an external reference oscillator is used. The device typically achieves 34dBc of carrier and sideband suppression at a -1dBm output level. The wideband, internally matched RF output can also be disabled while the synthesizer and 3-wire bus remain powered up for continuous programming. The device consumes 72mA from a single +3.0V supply and is packaged in an ultra-compact 28-pin QFN package (5mm 5mm) with an exposed pad. Single Voltage Supply (2.7V to 3.6V) 75MHz 3dB I/Q Input Bandwidth Wideband 50 RF Output: 700MHz to 2300MHz Ultra-Fine Frequency Resolution: 100mHz High Reference Frequency for Fast-Switching Applications Ultra-Low Phase Noise Low Spurious and Reference Emissions -1dBm RMS Output Power 60dB RF Muting Control 34dBc Typical Carrier Suppression 34dBc Typical Sideband Suppression Software- and Hardware-Controlled Shutdown Modes
Features
MAX2150
Ordering Information
PART MAX2150ETI MAX2150ETI+ TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 Thin QFN-EP* 28 Thin QFN-EP*
Applications
Wireless Broadband Satellite Uplink LMDS Wireless Base Station
*EP = Exposed paddle. +Denotes lead-free package.
Pin Configuration/ Functional Diagram
VCC_RF I+ IQ+ QBUFEN BUFOUT
28
27
26
25
24
23
22
TXEN VCC_PA RFOUT N.C. N.C. LOCK VCC_SD
1 2 3 4 5 6 7
0
21 LO+ 20 LO19 VCC_LO 18 VCC_D
90
MAX2150
- MOD PROGRAMMING AND CONTROL
1/N PFD 1/R CHP
17 VCC_A 16 CHP 15 VCC_CHP
8
CLK
9
DATA
10
EN
11
SHDN
12
13
14
SYNEN OSCIN VCC_XTAL
QFN
________________________________________________________________ Maxim Integrated Products
1
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
ABSOLUTE MAXIMUM RATINGS
VCC to GND ...........................................................-0.3V to +6.0V RF Signals: LO+, LO-, OSCIN ........................................+10dBm I+ to I-, Q+ to Q-.......................................................................2V LO+, LO-, I+, I-, Q+, Q-, BUFEN, TXEN, CLK, DATA, EN, SYNEN, OSCIN, OSCOUT, BUFOUT, CHP, SHDN, LOCK, VCC_CP to GND..............-0.3V to (VCC + 0.3V) Digital Input Current .........................................................10mA Short-Circuit Duration RFOUT, BUFOUT, OSCOUT, Lock, CHP...........................................................................10s Continuous Power Dissipation 28-Pin TQFN (TA = +70C)..................................................2W (derate 28.5mW/C above +70C) Operating Temperature Range ...........................-40C to +85C Junction Temperature Range ..........................................+150C Storage Temperature.........................................-65C to +150C Lead Temperature (soldering 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX2150 EV kit. VCC = +2.7V to +3.6V, GND = 0V, SHDN = PLLEN = TXEN = high, BUFEN= low. No AC input signals. RFOUT and BUFOUT output ports are terminated in 50. TA = -40C to +85C. Typical values are at VCC = +3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER SUPPLY Supply Voltage TX mode, SHDN = PLLEN = TXEN = high BUFEN = low Supply Current SYNTH mode, SHDN = PLLEN = high, TXEN = BUFEN = low MOD mode, SHDN = TXEN = high, SYNEN = BUFEN = low LO Buffer Supply Current Shutdown Supply Current Additional current in all modes for BUFEN = high HW_SHDN mode, SHDN = low SW_SHDN mode, PWDN bit at logic low 2 0.5 1 -1 2 0.5 MOD mode MOD mode VCC 0.5 0.5 1 -1 25 1 2.7 3 72 25 46 3.3 0.3 35 3.6 107 38 69 5.5 600 600 mA A mA V CONDITIONS MIN TYP MAX UNITS
CONTROL INPUT/OUTPUTS (SHDN, TXEN, SYNEN, BUFEN) Input Logic High Input Logic Low Input Logic High Current Input Logic Low Current Lock Detect High (Locked) Lock Detect Low (Unlocked) Power-Up Time Power-Down Time V V A A V V s s
3-WIRE CONTROL INPUT (CLK, DATA, EN) Input Logic High Input Logic Low Input Logic High Current Input Logic Low Current V V A A
2
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer
AC ELECTRICAL CHARACTERISTICS
(MAX2150 EV kit. VCC = +2.7V to +3.6V, SHDN = PLLEN = TXEN = high, BUFEN =low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output ports are terminated in 50 loads. fLO =1750MHz, PLO = -10dBm, typical values are at VCC = +3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER MODULATION INPUT I/Q Input Bandwidth I/Q Differential Input Level I/Q DC Input Resistance I/Q Common-Mode Input Range RF OUTPUT Frequency Range Output Power Output 1dB Compression Point Output IP3 Carrier Suppression Sideband Suppression RF Output Noise Floor Output Return Loss LO INPUT/OUTPUT Frequency Range LO Input Power LO Input Return Loss LO Buffer Output Level (Note 2) fLO =2000MHz BUFEN = high (Note 2) -14 700 -12 -10 -15 -9.5 2300 -7 MHz dBm dB dBm fRF = 1750MHz fLO - fI/Q, fRF = 1750MHz fOFFSET > 40MHz (Note 2) (Note 3) 25 TXEN = high, fRF = 1750MHz TXEN = low, fRF = 1750MHz 700 -7 -1 -60 1 14 34 34 -148 -9 -143 2300 MHz dBm dBm dBm dBc dBc dBm/Hz dB (Note 2) 1.5 BW (-1dB) BW (-3dB) Assumes a sine-wave input to achieve the RFOUT output power specified below 26 75 1 200 1.6 1.7 MHz VP-P k V CONDITIONS MIN TYP MAX UNITS
MAX2150
SIGMA-DELTA FRACTIONAL-N SYNTHESIZER SYSTEM REQUIREMENTS Frequency Range Phase-Detector Input-Referred Phase Noise Floor In-Loop Spurious Emissions (Note 2) fCOMP = fREF = 20MHz, CP0 = CP1 = CPX = 1 (Note 4) fLO = 1740.005MHz, fCOMP = fREF = 20MHz, CP0 = CP1 = CPX = 1 (Note 5) 700 -138 -40 2300 MHz dBc/Hz dBc
MAIN DIVIDER AND PHASE DETECTOR Minimum Fractional-N Step Size Phase-Detector Comparison Frequency Maximum N Division Minimum N Division fCOMP/ 228 20 251 35 30 MHz
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2150 EV kit. VCC = +2.7V to +3.6V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output ports are terminated in 50 loads. fLO =1750MHz, PLO = -10dBm, typical values are at VCC = +3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER REFERENCE OSCILLATOR AND DIVIDER Input Frequency Range AC-Coupled Input Sensitivity Reference Division Ratio CHARGE-PUMP OUTPUT CP1, CP0 = 00 CP1, CP0 = 01 Charge-Pump Current (Note 7) CP1, CP0 = 10 CP1, CP0 = 11 Charge-Pump Voltage Compliance Sink/source currents match within 5% CPX = 0 CPX = 1 CPX = 0 CPX = 1 CPX = 0 CPX = 1 CPX = 0 CPX = 1 0.12 0.23 0.23 0.47 0.36 0.70 0.48 0.91 0.5 0.17 0.34 0.35 0.67 0.52 1.00 0.69 1.31 0.22 0.44 0.46 0.88 0.68 1.30 0.90 1.70 VCC 0.5 V mA AC-coupled, single ended (Note 2) (Notes 2, 6) 10 0.4 1 50 2.3 4 MHz VP-P CONDITIONS MIN TYP MAX UNITS
Note 1: Parameters are guaranteed by production testing at +25C and +85C. Minimum and maximum values over the temperature and supply voltage range are guaranteed by design and characterization. Note 2: Guaranteed by design and characterization. Note 3: Measured with MAX2150 EV kit. Note 4: Measured with an on-chip crystal oscillator. Note 5: In-loop spurious emissions occur when synthesizing a frequency at an integer multiple of the comparison frequency with fractional offset within the PLL loop BW. Note 6: If an on-chip oscillator is used, a fundamental tone crystal is needed. Note 7: Minimum and maximum values at CPX = 1 are guaranteed by production testing. Values at CPX = 0 are guaranteed by design and characterization.
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer
Typical Operating Characteristics
(MAX2150 EV kit. VCC = +3V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output ports are terminated in 50 loads. fLO =1750MHz, PLO = -10dBm, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX2150 toc01
MAX2150
MODULATION OUTPUT POWER vs. FREQUENCY
MAX2150 toc02
MODULATION OUTPUT POWER vs. FREQUENCY
TXEN = LOW MODULATION OUTPUT POWER (dBm)
MAX2150 toc03
100 TX MODE 80 SUPPLY CURRENT (mA) +85C +25C
4 TXEN = HIGH MODULATION OUTPUT POWER (dBm) 2 -40C 0 -2 -4 -6 -8 -10 -12 700 1100 1500 FREQUENCY (MHz) 1900 +85C +25C
-55
-58 -40C -61 +25C -64 +85C -67
60
-40C
40
20
0 2.7 3.0 3.3 3.6 SUPPLY VOLTAGE (V)
-70 2300 700 1100 1500 FREQUENCY (MHz) 1900 2300
OUTPUT POWER vs. LO POWER
MAX2150 toc04
CARRIER AND SIDEBAND SUPPRESSIONS vs. LO POWER
MAX2150 toc05
MODULATOR OUTPUT POWER vs. I/Q INPUT LEVEL
MODULATOR OUTPUT POWER (dBm)
MAX2150 toc06
-1.1 -1.2 OUTPUT POWER (dBm) -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2.0 7 8 9 10 11
CARRIER AND SIDEBAND SUPPRESSIONS (dB)
-1.0
38 37 36 SIDEBAND SUPPRESSION 35 34 CARRIER SUPPRESSION 33 32
4 0 -40C -4 +25C -8 -12 -16 -20 -24
+85C
12
7
8
9
10
11
12
0
200
400
600
800 1000 1200 1400
LO POWER (dBm)
LO POWER (dBm)
I/Q INPUT LEVEL (mV)
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
Typical Operating Characteristics (continued)
(MAX2150 EV kit. VCC = +3V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output ports are terminated in 50 loads. fLO =1750MHz, PLO = -10dBm, TA = +25C, unless otherwise noted.)
LO PORT INPUT RETURN LOSS vs. FREQUENCY
MAX2150 toc08 MAX2150 toc09
MODULATOR OUTPUT IP3 vs. VCC
+85C
MAX2150 toc07
MODULATOR OUTPUT P1dB vs. VCC
3.0 MODULATOR OUTPUT P1dB (dBm) 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -40C +85C +25C 0 -5 -10 -15 -20 -25 -30 2.7 3.0 VCC (V) 3.3 3.6 700
16 MODULATOR OUTPUT IP3 (dBm) 15 14 13 12 -40C 11 10 2.7 3.0 VCC (V) 3.3
+25C
LO PORT RETURN LOSS (dB)
3.6
1100
1500 FREQUENCY (MHz)
1900
2300
BUFOUT PORT RETURN LOSS vs. FREQUENCY
MAX2150 toc10
LO BUFFER OUTPUT POWER vs. FREQUENCY
MAX2150 toc11
LO BUFFER OUTPUT POWER vs. FREQUENCY
BUFEN = LOW LO BUFFER OUTPUT POWER (dBm) -43
MAX2150 toc12
0 BUFOUT PORT RETURN LOSS (dB) -5 -10 -15 -20 -25 -30 700 1100 1500 FREQUENCY (MHz) 1900
-4 -5 LO BUFFER OUTPUT POWER (dBm) -6 -7 -8 -9 -10 -11 -12 -13 -14 -40C +25C BUFEN = HIGH
-40
+85C
-46 +85C
+25C
-49
-52
-40C
-55 700 1100 1500 FREQUENCY (MHz) 1900 2300 700 1100 1500 FREQUENCY (MHz) 1900 2300
2300
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer
Typical Operating Characteristics (continued)
(MAX2150 EV kit. VCC = +3V, SHDN = PLLEN = TXEN = high, BUFEN = low. Input I/Q signals: FI/Q = 500kHz, VI/Q = 1VP-P. I+, Q+ single-ended input, driven from AC-coupled source. I-, Q- single-ended inputs are AC-coupled to GND. RFOUT and BUFOUT output ports are terminated in 50 loads. fLO =1750MHz, PLO = -10dBm, TA = +25C, unless otherwise noted.)
OSCIN PORT SENSITIVITY (SYNTHESIZER) vs. FREQUENCY
6 5 4 3 +25C 2 +85C 1 -40C 0 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz) 0 0.10 0.20 -40C +25C +85C 0.30
MAX2150 toc13
MAX2150
OSCIN IMPEDANCE vs. FREQUENCY
-100 OSCIN PORT IMPEDANCE () REAL
MAX2150 toc14
0.60 0.50 0.40
0
OSCIN PORT SENSITIVITY (V)
-200 -300 -400 -500 -600 -700 -800 -900 IMAGINARY
-1000 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz)
SYNTHESIZER PHASE NOISE
MAX2150 toc15
I/Q MODULATOR OUTPUT SPURS
0 -10 -20 -30 -40 -50 1 AVG
MAX2150 toc16
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 CENTER = 1.75MHz SPAN = 20kHz N/C = -99dBc/Hz -8.5dBm
CARRIER SUPPRESSION -34dBc SIDEBAND SUPPRESSION -36dBc
-60 -70 -80 -90 -100 CENTER = 1.75 GHz SPAN = 2 MHz
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
Pin Description
PIN 1 2 3 4, 5 6 7 8, 9, 10 11 12 NAME TXEN VCC_PA RFOUT N.C. LOCK VCC_SD CLK, DATA, EN SHDN SYNEN FUNCTION Modulator Enable Input. Set TXEN low to inhibit the RF and modulator circuits. This mode can be used for quiet frequency synthesis. Supply Voltage Input for RFOUT Output Driver Circuits. Bypass as close to the pin as possible. The bypass capacitor should not share ground vias with other branches. Modulator RF Output. This is a wideband, internally matched 50 output. A DC-blocking capacitor is required. Do Not Connect. (These pins must be left floating.) Lock Status of the PLL. A static logic-level high indicates that the PLL is in the locked condition. Supply Voltage Input for Sigma-Delta Modulator Circuits. Bypass as close to the pin as possible. The bypass capacitor should not share ground vias with other branches. Input Pins from 3-Wire Serial Bus. An RC lowpass filter on each of these pins can be used to reduce digital noise. Shutdown Control. Set SHDN low to disable all internal circuits for lowest power consumption. An RC lowpass filter can be used to reduce digital noise. Synthesizer Enable Input. Set SYNTH low to disable the internal frequency synthesizer. An RC lowpass filter can be used to reduce digital noise. Reference Oscillator Input. Connect a parallel, resonant, fundamental-tone crystal between this pin and ground to facilitate a crystal oscillator circuit. For applications with an external reference oscillator, the OSCIN input can be driven through a large-value series capacitor. Supply Voltage Input for Crystal Oscillator. Bypass as close to the pin as possible. The bypass capacitor should not share ground vias with other branches. Supply Voltage Input for Charge Pump. Bypass as close to the pin as possible. The bypass capacitor should not share ground vias with other branches. High-Impedance Charge-Pump Output. Connect to the tune input of the VCO through the PLL loop filter. Keep the line from this pin to the tune input as short as possible to prevent spurious pickup, and connect the loop filter as close to the tune input as possible. Supply Voltage Input for PLL. Bypass as close to the pin as possible. The bypass capacitor should not share ground vias with other branches. Supply Voltage Input for PLL. Bypass as close to the pin as possible. The bypass capacitor should not share ground vias with other branches. Supply Voltage Input for Internal LO Circuits. Bypass as close to the pin as possible. The bypass capacitor should not share ground vias with other branches. Differential Local-Oscillator Input. These inputs require DC-blocking capacitors. The LO can be applied with a single-ended input to the LO+/LO- pin. In this mode, the other pin should be AC-grounded. Buffered LO Output. Internally matched to 50, requires a DC-blocking capacitor. LO Output Buffer Amplifier Enable. Set BUFEN high to enable the on-chip output LO buffer for driving external circuits. An RC lowpass filter can be used to reduce digital noise. Differential Q-Channel Baseband Inputs to the Modulator. These pins connect directly to the bases of a differential pair and require an external common-mode bias voltage of 1.6V.
13
OSCIN
14 15
VCC_XTAL VCC_CHP
16
CHP
17 18 19 20, 21 22 23 24, 25
VCC_A VCC_D VCC_LO LO-, LO+ BUFOUT BUFEN Q-, Q+
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer
Pin Description (continued)
PIN 26, 27 28 -- NAME I-, I+ VCC_RF FUNCTION Differential I-Channel Baseband Inputs to the Modulator. These pins connect directly to the bases of a differential pair and require an external common-mode bias voltage of 1.6V. Supply Voltage Input for RF Circuits. Bypass as close to pin as possible. The bypass capacitor should not share ground vias with other branches.
MAX2150
Exposed pad Ground
Detailed Description
Internally, the MAX2150 includes a broadband I/Q modulator, internally matched broadband output driver amplifier, fine-resolution fractional-N frequency synthesizer, an LO buffer amplifier, and an on-chip low-noise crystal oscillator circuit. A simple 3-wire interface is provided for synthesizer programming and device configuration and control. Independent hardware and software power-down control of the I/Q modulator, frequency synthesizer, and LO buffer amplifier is provided, as well as the ability to shut down the entire chip.
The modulator can be shut down with both hardware (pin 1) and software (TE bit). This mode is useful for quiet synthesizer programming or to mute the RF output signal. The hardware pin and software bits must be set to logic-1 to enable the modulator. If the hardware pin or software bit is set to logic-0, or if both are set to logic-0, the modulator is disabled.
LO Buffer Amplifier
The broadband buffer amplifier output is internally matched and requires a DC-blocking capacitor to isolate on-chip bias voltages. Power-down of the LO buffer can be controlled by both BUFEN (pin 23), as well as BUFEN by software by setting the BUFEN (BE) bit through the 3-wire interface. The hardware pin and the software bit must be a logic-1 to enable the buffer. If the hardware or software bit is set to logic-0, the LO buffer is disabled.
I/Q Modulator
The MAX2150 modulator is composed of a pair of matched double-balanced mixers, a broadband passive LO quadrature generator, and a summing amplifier. The mixers accept differential I/Q baseband signals that directly modulate the internal 0 and 90 LO signals applied to the I/Q mixers. An external LO source drives an internal LO quadrature generator that shifts the phase of the LO signal applied to the Q mixer by 90 relative to the LO signal applied to the I-channel mixer. The modulated output of the I/Q mixers is summed together, and the undesired sideband is suppressed. The I+, I-, Q+, and Q- input ports feature high-linearity buffer amplifiers with a typical -3dB bandwidth of 75MHz and accept differential input voltages up to 1VP-P. The ports require external biasing and have an input common-mode requirement of 1.6V. For singleended operation, bypass the I and Q ports to ground. See the Typical Application Circuit for recommended component values. The broadband output driver amplifier is matched on chip across the entire operating frequency range and requires an output DC-blocking capacitor. For optimum performance, the output match can be improved with simple L-section and/or PI-section matching networks. Always ensure that DC blocking is provided, because internal bias voltages are present at this output.
Frequency Synthesizer
The MAX2150 features an internal 28-bit sigma-delta frequency synthesizer. This architecture enables the use of very high (30MHz) comparison frequencies, which significantly reduces the in-loop phase noise as a result of reduced division ratios. The high comparison frequency also allows significantly increased PLL bandwidths for very fast switching speed applications.
Divider Programming
The MAX2150 frequency programming is determined as follows. The overall division ratio (D) has an integer value (N), as well as a fractional component (F): D = N.F = N +F / 228 The N and F values are encoded as straight binary numbers. Determination of these values is illustrated by the following example: FLO = 1721.125MHz, FCOMP = 20MHz Then: D = 1721.125 / 20 = 86.05625 Therefore: N = 86 and F = 0.05625 x 228 = 15,099,494
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
Converting each to binary representation results in the following: N register = 86 = 0101,0110 F register value = 0000,1110,0110,0110,0110,0110,0110 The F-register value is then split between an upper 14 bits and a lower 14 bits as follows: Upper 14 bits + address 00 = 0000,1110,0110,0100 Lower 14 bits + address 01 = 1001,1001,1001,1001
Fractional Spurs
When synthesizing a frequency that is an integer multiple of the reference divider and having a fractional offset with a value less than the PLL filter bandwidth, fractional spurs can be observed at a typical level of -40dBc. For example, to synthesize 1640.005MHz when using a 20MHz reference and a PLL bandwidth of 25kHz, spurious products offset from the LO by 5kHz can be observed. The 1640MHz is an integer multiple of 20MHz, and the fractional offset of 5kHz is within the PLL bandwidth. It is possible to avoid the above-mentioned spurious products by using two reference oscillators with slightly offset frequencies or by using a higher reference frequency and changing the comparison frequency of the reference divider.
Synthesizer Shutdown
The synthesizer can be disabled by setting SYNEN (pin 12) to a logic low. This mode is useful when an external frequency synthesizer is employed.
Applications Information
Serial Interface and Register Definition
3-Wire Interface and Registers The MAX2150 is programmed through a simple 3-wire (CLK, DATA, EN) interface. The programming data is contained within 16-bit words loaded into four unique address locations. Each location contains programming information for setting operational modes and device configuration. Two words (address 00, 01) control the fractional divide number in the sigma-delta synthesizer. The third word (address 10) sets the integer divide value, reference divide value, charge-pump current, and charge-pump compensation DAC settings. The fourth and final word (address 11) contains various device configuration registers and test registers, as well as additional charge-pump compensation registers. See Tables 1 through 11 for details. 3-Wire Interface Timing Diagram Figure 1 shows the programming logic. The 16-bit shift register is programmed by clocking in data at the rising edge of CLK. Pulling enable low allows data to be clocked into the shift register; pulling enable high loads the register addressed.
Crystal Oscillator
The MAX2150 includes a simple-to-use on-chip lownoise reference oscillator circuit. The oscillator is formed by connecting a fundamental mode parallel resonant crystal from OSCIN to ground. The oscillator circuit is useful from 10MHz to 50MHz. The phase noise of the MAX2150 can be improved by using a precision high-frequency external reference oscillator (TCXO). The external oscillator is connected through a DC-blocking capacitor directly to the OSCIN pin.
Layout Considerations
A properly designed PC board is an essential part of any RF circuit. A ground plane is essential. Keep RF signal lines as short as possible to reduce losses, radiation, and inductance. The exposed pad on the underside of the MAX2150 must be adequately grounded by ensuring that the exposed paddle of the device package is soldered evenly to the board ground plane. Use multiple, low-inductance vias to ground the exposed paddle.
DATA
B19 (MSB)
B18
B0
A3
A1
A0 (LSB)
CLK tCWL tCS EN tEW tCH tCWH tES
tCS > 50ns tCH > 10ns tCWH > 50ns tES > 50ns tCWL > 50ns tEW > 50ns
Figure 1. 3-Wire Interface Timing Diagram 10 ______________________________________________________________________________________
Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
Table 1. Register Tables
MSB 27 13 26 12 25 11 24 10 23 9 SHIFT REGISTER DATA Upper (MSBs) Fractional Divider Value (F) 14 Bits (Default = 8192, 10000000000000) 22 8 21 7 20 6 19 5 18 4 17 3 16 2 15 1 14 0 0 Address 0 Address 1 0 1 Address CPX 1 1 0 1 Lower (LSBs) Fractional Divider Value (F)14 Bits (Default 0 DEC, 00000000000000 R Divider Default = 00 R1 R0 CP Bleed Default = 00 LIN1 LIN0 CP Current Default = 11 CP1 CP0 7 6 Integer Divide Value (N) 8 Bits Default = 177 DEC 5 4 3 2 LSB ADDRESS Address 0
Reset Delay Default = 00 BL1 BL0 T5 T4
Test Registers 6 Bits Default = 0 DEC T3 T2 T1 T0 INT
Control Register 6 Bits Default = 15 DEC PD TE BE XX
Table 2. Reference Divider
R1 0 0 1 1 R0 0 1 0 1 REFERENCE DIVIDE VALUE 1 2 3 4
Table 3. Integer Divider-N*
N7 0 0 -- 1 1 N6 0 0 -- 1 1 N5 1 1 -- 1 1 N4 0 0 -- 1 1 N3 0 0 -- 1 1 N2 0 1 -- 0 0 N1 1 0 -- 1 1 N0 1 0 -- 0 1 INTEGER DIVIDE VALUE 35 36 -- 250 251
*N divider is limited to 35 < N < 251.
Table 4. Fractional Divider-F (Upper 14 Bits)
F27 0 0 -- 1 F26 0 0 -- 1 F25 0 0 -- 1 F24 0 0 -- 1 F23 0 0 -- 1 F22 0 0 -- 1 F21 0 0 -- 1 F20 0 0 -- 1 F19 0 0 -- 1 F18 0 0 -- 1 F17 0 0 -- 1 F16 0 0 -- 1 F15 0 0 -- 1 F14 0 0 -- 1
Table 5. Fractional Divider-F (Lower 14 Bits)
F13 0 0 -- 1 1 F12 0 0 -- 1 1 F11 0 0 -- 1 1 F10 0 0 -- 1 1 F9 0 0 -- 1 1 F8 0 0 -- 1 1 F7 0 0 -- 1 1 F6 0 0 -- 1 1 F5 0 0 -- 1 1 F4 0 0 -- 1 1 F3 0 0 -- 1 1 F2 0 0 -- 1 1 F1 0 0 -- 1 1 F0 0 1 -- 0 1 INTEGER DIVIDE VALUE 1 2 -- 268435454 268435455
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Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
Table 6. Control Register
BIT ID BIT NAME CP_MULT XX BUFEN TXEN PWDN INT_MODE PWR-UP STATE 1 XX 1 1 0 0 BIT LOCATION 0 = LSB 0 1 2 3 4 5 FUNCTION A logic high doubles the charge pump current selected through registers CP1 and CP0. Logic low sets the charge-pump current to the value selected by registers CP1 and CP0. Unused. High enables the VCO buffer. Low disables this output. Low enables SW_MUTE mode, which shuts down the RF circuits while leaving the 3-wire interface, register, and PLL circuits active. Low enables register-based shutdown. This mode shuts down all circuits except the 3-wire interface and internal registers. Logic high disables the sigma-delta modulator. Logic low enables the sigma-delta modulator for normal operation.
CPX XX BE TE PD INT
Table 7. Device Modes
MODE SHDN TX MOD H H HW PINS TXEN H H SYNEN H L BUFEN H/L H/L SOFTWARE CONTROL BITS PWDN TXEN BUFEN H H H H H/L H/L DESCRIPTION All circuits active. Modulator circuits active. Synthesizer blocks disabled. Mode is used with external PLL circuit. Serial interface and synthesizer blocks active. RF and modulator blocks disabled. Mode is used to gate RF ON/OFF with external logic control. Serial interface and synthesizer blocks all active. Modulator blocks disabled. Mode is used to gate RF ON/OFF with software control. All circuits disabled. Lowest current mode of operation. Serial interface and registers active, all other circuits inactive regardless of the state of the HW pins with the exception of HW_SHDN.
SYNTH
H
L
H
H/L
H
X
H/L
SW_MUTE
H
H
H
H/L
H
L
H/L
HW_SHDN
L
X
X
X
X
X
X
SW_SHDN
H
X
X
X
L
X
X
Power-Supply (VCC) Bypassing Proper voltage-supply bypassing is essential to reduce the spurious emissions mentioned above. It is recommended that each VCC pin be bypassed independently
and share no common vias with any other ground connection. See the Typical Operating Circuit for suggested bypass component values.
12
______________________________________________________________________________________
Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
Table 8. TXEN Pin and Software Bit Definitions
TXEN PIN 0 0 1 1 BIT 0 1 0 1 TX MODE TX off TX off TX off TX enabled
Table 11. BUFEN Pin and Software Bit Definitions
BUFEN PIN 0 0 1 1 BIT 0 1 0 1 BUF MODE Buffer off Buffer off Buffer off Buffer on
Table 9. Charge-Pump Registers
CPX 0 0 0 0 1 1 1 1 CP1 0 0 1 1 0 0 1 1 CP0 0 1 0 1 0 1 0 1 ICP (A) 170 350 520 690 340 670 1000 1310
Chip Information
TRANSISTOR COUNT: 16,321
Table 10. Test Register Definition (Default 0 Dec)*
TEST MODE Normal Operating Mode Charge Pump Forced to Source Icp Charge Pump Forced to Sink Icp Reference Divider Output Main Divider Output T5 0 T4 0 T3 0 T2 0 T1 0 T0 0 TEST PIN --
0
0
0
0
0
1
CP
0
0
0
0
1
0
CP
0 0
1 1
0 1
0 0
0 0
0 0
Lock Lock
*All other logic states are undefined.
______________________________________________________________________________________
13
Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
Typical Operating Circuit
J1 31-5239-52RFX I C50 0.1F VCC R31 3.3k R32 3.3k R33 3.3k R34 3.3k C2 100pF R1 OPEN R2 OPEN R3 OPEN R4 OPEN C1 0.1F BUFEN VCC IN J2 31-5239-52RFX Q C52 0.1F QN
R29 OPEN DCIN C28 0.1F
VCC J6 VCC J7 GND 1 VCC C17 100pF 2 VCC_PA LO20 C8 22pF VCC 3 C16 OPEN J16 4 TEST2 RFOUT VCC_LO 19 1 VT GND C12 100pF C20 0.1F C25 1F C31 0.1F 28 VCC_RF TXEN 27 I+ 26 I25 Q+ 24 Q23 BUFEN 22 BUFOUT LO+ 21 C7 OPEN C32 0.1F J15 LOn C3 0.1F VCC R12 0 C5 OPEN C6 OPEN C33 0.1F J13 BUFOUT
J14 LO
J8 RFOUT
R13 0 C15 OPEN
C18 0.1F
U2 VC3R0A230967/ 1750B350FUJI 7 6 GND VSW GND 5 4
U1 MAX2150
VCC_D 18
VCC
C4 100pF
2 3
VCC J17 5 TEST1 VCC_A 17 C11 100pF 16
C10 100pF
VCC GND OUT 8
VCC_VCO J19 J5 VCCVCO J11 GND
LOCK J20
6
LOCK
CHP
VCC VCCSD C27 1.0F 7 C14 100pF 15
C22 6800pF VCC VCC_SD CLK 8 DATA 9 EN JUMP_PAD EN 10 SHDN 11 SHDN SYNEN 12 OSCIN 13 VCC_CHP VCC_XTAL 14 C9 100pF
C35 100pF
C34 0.1F
C19 0.1F
R24 1.1k
R25 1.1k
R23 245 VCC C23 .068F
C37 VCC 0.1F C13 100pF
C24 680pF
C26 470pF R35 OPEN
L1 OPEN
C21 0.1F
VTUNE_OUT TUNEOUT
FILTVCC
VCOSEL
SHDNn
SYNEN
LOCK
DATA
TXEN
C36 0.1F
R18 0 C30 0.1F
Y1
CLK J10-5
J10-1
J10-3
J10-7
ENn
J10-13
J10-15
J10-17
J10-11
J10-19
J10-9
J18 REFL In
J10-12
J10-2
J10-4
J10-6
J10-14
J10-16
J10-18
14
______________________________________________________________________________________
J10-10
J10-20
J10-8
Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
32L QFN.EPS
MAX2150
______________________________________________________________________________________
15
Wideband I/Q Modulator with Sigma-Delta Fractional-N Synthesizer MAX2150
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2006 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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